Proposal of a logic compatible merged-type gain cell for high-density embedded DRAM's

A new structure is proposed for a logic compatible merged-type DRAM gain cell, and device and process simulations are performed to verify the cell operation. This cell enables the realization of the memory cell without direct use of capacitor, and is almost compatible with a conventional CMOS logic process. Therefore, it does not require new materials nor new processing equipment, and can be realized in less than 5% increase in process steps in comparison to the 50%-60% increase or more for logic embedded DRAM's with a one-capacitor+one-transistor cell. It can drastically improve "1" and "0" states' separation due to JFET ON/OFF effect of an n-channel region between two p/sup +/-gate regions. For the investigation of the proposed gain cell, detailed simulation is performed utilizing the simulation system well tuned to the actual 0.25-/spl mu/m logic process technology. Furthermore three transistors are merged into approximately one transistor area minimizing the cell size to almost one transistor area. Nondestructive read-out (NDRO) is possible resulting in smaller read cycle time since it does not need re-writing after reading-out, Smaller access time is also possible due to current sensing instead of charge sensing.