Occurrence and elimination of anomalous temperature dependence of latchup trigger currents in BiCMOS processes

Latchup trigger currents in a BiCMOS process show an extreme temperature dependence (from >100 mA to <3 mA with /spl Delta/T=1/spl deg/C), severely affecting product latchup susceptibility. The effect is strongly process and wafer fab dependent and caused by lifting of the substrate potential, primarily due to saturation of bipolar transistors, causing hole injection and subsequent turn-on of parasitic n-type field transistors. The effect can be eliminated by a combination of process and design measures. The use of a buried-P layer or of low ohmic (/spl les/1 /spl Omega/cm) substrates is especially effective. For qualification purposes, a 30/spl deg/C test temperature guard-banding is needed to take the effect into account.