Device level modeling challenges for circuit design methodology in presence of variability

CMOS technology scaling to decananometer range has raised the challenge to mitigate the impact of multi-scale process variations ranging from cm to atom-scale and acting as circuit yield detractors. Moreover, circuit applications in Ultra Low Power (ULP) range lead to MOSFET device operation in near threshold regime where it is well established that variability impact on DC/AC electrical characteristics dramatically increases. Variability mitigation techniques are part of process development. In addition, accurate circuit design methodologies are required to determine circuit performance margins versus specifications, and to develop circuit level variability mitigation/compensation techniques, to enable high yield and manufacturable products in presence of variability. In this context, we update device modeling requirements for circuit design, revisit device electrical characterization and compact modeling methodologies needed to support accurate circuit simulation throughout the design space. We focus on spatial variability components at local scale, including systematic layout effects and statistical variability. This approach is illustrated on UTBB FDSOI devices. Device modeling challenge for accurate circuit simulation in presence of variability is better identified.