Fail-soft Circuit Design In A Cache Memory Control LSI

This paper describes a realtime-degradable 4-way set-associative cache memory control LSI. Three kinds of errors, address parity error, comparator error, and multihit error can cause functional degradation[1] by killing the associative unit corresponding to the fault location. A 20-bit tag parity generator, a double comparator, and a multihit detector are the key circuit for the falut deterction. The parity generator and the double comparator have no effect on the timing-sensitive path delay because of the parallel configuration of the circuits.