Data-line wiring delay reduction techniques for high-speed BiCMOS SRAM's

For scaled BiCMOS SRAM's distributed RC line delay, caused by long data-line wiring, seriously degrades speed merit of a BiCMOS sense-amplifier against a CMOS one. This paper describes and discusses circuit techniques of eliminating the data-line wiring delay, Performance for a 0.2ns 1Mb TTL SRAM test chip implementing one of those techniques is also presented.