Advances in steep-slope tunnel FETs

Tunnel FETs (TFETs) with steep subthreshold slope have been attracting much attention as building blocks for future low-power integrated circuits and CMOS technology devices. Here we report on recent advances in vertical TFETs using III–V/Si heterojunctions. These heterojunctions, which are formed by direct integration of III–V nanowires (NWs) on Si, are promising tunnel junction for achieving steep subthreshold slope (SS). The III–V/Si heterojunction inherently forms abrupt junctions regardless of precise doping technique because the band discontinuity is determined by only the offset of III–V and Si, and depletion region can be controlled by the III–V MOS structure. Thus, good gate-electrostatic control with a large internal electrical field for modulation of tunnel transport can be achieved. Here we repot on recent advances in the vertical TFETs using the III–V NW/Si heterojunction with surrounding-gate architecture and demonstrate steep-SS behavior and very low parasitic leakage current.