Floating gate memory based on MoS2 channel and iCVD polymer tunneling dielectric

We investigated the floating gate memory based on MoS
2
channel with metal nanoparticle charge trapping layer and polymer tunneling dielectric. Here, highly conformal and stable polymer insulator layer deposited via initiated chemical vapor deposition (iCVD) facilitates the fabricated floating gate memory to endure a substantial electrical stress significantly. To form a selective density and controllable distribution of charge trapping layer, different thickness of gold nanoparticles via thermal evaporation method was used. Al
2
O
3
blocking dielectric is deposited via atomic layer deposition (ALD) process to increase gate coupling ratio for low power operation. The fabricated floating gate memory device exhibits tunable memory window with a high on/off ratio after applied programming and erasing pulse, allowing for multi-bit data storage with a long retention I
on/off
ratio. All these results will be a foundation stone for the development of floating gate memory based on MoS
2
.