On-chip I–V variability and random telegraph noise characterization in 28 nm CMOS

Building reliable mixed-signal circuits in advanced process technologies requires an accurate understanding of device performance and variability. This work presents an on-chip transistor characterization platform built on a digital focal plane array readout circuit framework that enables highly parallel device measurements to be taken in the digital domain. This technique is used to quickly assess large-scale transistor characteristics and study the impact of random telegraph noise (RTN) in deeply scaled technologies. A 28 nm HKMG bulk LP CMOS test chip containing over 80,000 NFETs and PFETs of multiple sizes and threshold voltages was fabricated and tested to study device parameters and RTN performance down to cryogenic temperatures. Results support previous studies of RTN temperature dependence and suggest that threshold voltage has minimal impact on RTN relative to device type and dimension.