A 4-cycle-start-up reference-clock-less all-digital burst-mode CDR based on cycle-lock gated-oscillator with frequency tracking

This paper proposes a reference-clock-less burst-mode CDR that resumes from a stand-by state just after a 4-bit preamble utilizing a cycle-lock gated-oscillator based on self-tunable digitally-controlled delay lines. Since the proposed CDR consumes no dynamic power in its stand-by state, it can improve the total power efficiency of serial communication systems that work intermittently such as mobile and IoT sensor node applications. The proposed frequency tracking architecture with fractional delay control scheme improves CID and jitter tolerance, and achieves 292 bits of CID tolerance. A prototype implemented in a 65 nm FD-SOI CMOS process operates at 1.2–2.3Gbps continuous rate with PRBS31 input. It consumes 11–21mA in its active state and 30 µA leakage current in its stand-by state from a 1.2V supply.