A 2 GHz 3.1 mW type-I digital ring-based PLL

This paper presents a type-I digital ring-based PLL with wide loop bandwidth to lower the ring oscillator's noise contribution. The in-band noise is addressed using a SAR-ADC-based sampling phase detector (SPD). A stacked reference buffer is also introduced to reduce the transient short-circuit current for low power and low reference spur. The loop delay due to the D flip-flops at filter's output is compensated in order to lower the noise peak, and stably achieve the wide loop bandwidth. The locking issue due to the static phase error in a type-I PLL and the limited range of the PD is addressed using a TDC-assisted loop. The prototype PLL fabricated in 65 nm CMOS demonstrates 2.4 ps RMS jitter, 3.1 mW power consumption, and 0.067 mm
²
area, with 50 MHz reference frequency and 2.0 GHz output frequency.