Performance of ATM switch using speedup networks

The biggest hurdle that faces the use of ATM for voice communication is cell delay and delay variance. This architecture utilizes the speedup concept where faster internal links and the availability of small internal queues reduce both blocking probability and cell delay. Adequate performance can be obtained using a speedup factor of 4 and internal queues of size 4. This work also presents the analytical and simulation models built to evaluate the performance. This work also studies the multicasting capability of this architecture. Finally, a high-level hardware implementation is described.