Verification system interface for VLSI combinational circuits

Proof of correctness of a given VLSIC system design is established by proving the consistency and implication of the implemented design with respect to the specified design. The set of conditions that establish such consistency is termed verification conditions (VCs). This paper presents an automatic interface system for the verification of VLSI combinational circuits in which VCs are synthesized from circuit definition. This interface will allow a top down specification of the design (written in a given HDL language) to be parsed into binary tree structure representation. Also, a logical construct is built up from the physical layout specifications of the implemented design (extracted as SPICE file). The top down parse tree along with bottom up logic constructs form the basic building block structure of the front end of the interface system. VCs are then synthesized from the outcomes of the front end through a preprocessor. The back end of the interface system constitutes the preprocessor and a set of designators and modules for manipulating mathematical and logical operations. It provides an environment in which a theorem prover can be used to create a formal proof schema for the VCs which satisfy partial correctness of the circuit under consideration.