Low switching noise CMOS circuit design strategy based on regular self-timed structures

In this paper a new design strategy used to implement low switching noise digital circuits is presented. The switching noise reduction is achieved by controlling the shape of the switching current waveform of the CMOS logic circuits. Self-timed structures are required to obtain the wanted switching current waveform shape. Current limiters are also used to control the current waveform amplitude of the single cells of the structure. The design strategy proposed is applied to a circuit example, a 4/spl times/4 unsigned array multiplier, and experimental results are presented.