A sub-40 ns random-access chain FRAM architecture with a 768 cell-plate-line drive

This work demonstrates a prototype of nonvolatile chain ferroelectric RAM (chain FRAM), with fast compact cell-plate-line drive. A 16 kb chain FRAM test chip using 0.5 /spl mu/m 2-metal CMOS achieves 37 ns random-access time and 80 ns read/write cycle time at 3.3 V.