450 MHz PowerPC/sup TM/ microprocessor with enhanced instruction set and copper interconnect

This superscalar microprocessor implements the PowerPC/sup TM/ Architecture specification incorporating AltiVec/sup TM/ technology. Two instructions per cycle can be dispatched to two of seven execution units in this microarchitecture designed for high execution performance, high memory bandwidth, and low power. The processor includes 8-way set-associative 32 KB instruction and data caches, a floating-point unit, two integer units, a branch unit, a load/store unit, a vector arithmetic/logic unit, a vector permute unit, and a system unit. An L2 tag and cache controller with a dedicated L2 bus interface supports L2 cache sizes of 512 KB, 1MB, or 2 MB with 2-way set associativity. At 450 MHz, and with a 2M B L2 cache, this processor is estimated to have a SPECint95 and SPECfp95 performance of 20. The processor shares many microarchitectural features with the PowerPC 750/sup TM/ microprocessor. New to this processor are two vector execution units which are part of the AltiVec/sup TM/ instruction set implementation, memory subsystem bandwidth enhancements, symmetric multiprocessing support and improved floating-point performance. Supporting up to 8 simultaneous data cache misses, the memory subsystem sustains bandwidths of 3.2 GB/s on the L2 data SRAM interface running at 200 MHz or 1.6 GB/s on the system interface running at 100 MHz.