A Two-Step Prediction ADC Architecture for Integrated Low Power Image Sensors

This paper presents a two-step prediction method for the design of low-power column-parallel analog-to-digital converters (ADC) in CMOS image sensors. The proposed prediction method takes advantage of the spatial likelihood of natural scenes, which shows strong correlations between neighboring pixels in the image. Based on this property, the proposed method predicts the MSBs of the selected pixel using quantization results of the neighboring pixels in the previous row, which enables a significant power reduction of the A/D conversions. The simulation results show that up to 20∼30% power saving can be achieved for most natural scenes. A 384
$\times$
256-pixel prototype chip was fabricated using a 0.35
$\mu\text{m}$
CMOS technology with a pixel footprint of
$15\ \mu\text{m} \times 15\ \mu\text{m}$
. The fill factor is 49%. 10-bit successive approximation register (SAR) ADCs are used in the column-parallel ADC array.