Characterization of 2.5D package warpage through Shadow Moiré technique and failure analysis

For the last few decades semiconductor industry has been following Moore Law effectively, which has resulted in significant miniaturization of transistors and chip logic circuitry, and the development of 3D integration technology. While due to the large size and extremely thin of chip and interposer, increasingly attention has been payed to the warpage, which was regarded not only decide the assembly process, but also affect the reliability of the package. In this study, the warpage of high power processor chip, TSV interposer and substrate was investigated during the whole reflow process by shadow moiré. The warpage of interposer and substrate was found similar around the peak reflow temperature, and quite different with the warpage of chip. Thus the assembly process started with packaging interposer and substrate first and good bonding quality was found from failure analysis.