Via last TSV process for wafer level packaging

Through silicon via (TSV) technology offers a promising approach to achieve three dimensional integrated circuit integration. Via-last TSV process has the advantages of flexibility and lower cost. In this paper, we report our latest progress on wafer level packaging by via-last process. The 200mm device wafer was bonded with a carrier wafer. Then, the vertical TSV structure with aspect ratio of 3:1 was realized from the device wafer side. The silicon vias are insulated by low temperature PECVD silicon dioxide. All the process steps are obtained at the wafer level using the state-of-the-art facilities. Detailed considerations in the process are introduced. Dielectrics etching without photoresist protection is used. Two plating mechanisms are utilized to achieve a robust TSV structure. The via-last process provides a cost-effective solution for heterogeneous 3D integration.