10µm pitch Cu-Cu bonding interconnection for wafer level 3D integration

Three-dimensional (3D) integration is considered as a good alternative solution to overcome the limitations of silicon scaling. Through Silicon Via (TSV) and wafer bonding are two key elements for 3D integration. This paper focuses on the realization of high density direct bonding interconnection. Hybrid Cu-Cu and SiO
₂
-SiO
₂
bonding was chosen for direct inter-wafer interconnection. A mask set of Test-Vehicle (TV) was specifically designed to allow the electrical characterization of the hybrid Cu-Cu bonding. Inter wafer interconnection pitch as small as 10μm has been realized through hybrid Cu-Cu and SiO
₂
-SiO
₂
bonding on 300mm wafer. After bonding, one wafer of the bonded pair was thinned and the overall substrate was removed to exposure the metal pad for electrical characterization. Both bonding interconnection daisy chain and kelvin structure were used for electrical characterization. After linear fit, the average resistance for a single chain node is about 58.5mohm, which includes bond contact resistance and chain line resistance. For a contact node diameter of 5μm, the measured kelvin contact resistance is about 3.49 mΩ. Through calculation, the bonding contact resistance is about 68.5 mΩ-μm
²
, which is lower than reported researches. Cross section SEM also shows a good bonding interface.