Design and preliminary performance of a novel mixed-signal front-end electronics with post digital shaping for CZT detectors

This paper presents design and preliminary performance of a mixed-signal front-end electronics dedicated to CZT detectors. It is implemented by a full-customized readout application-specific integrated circuit (ASIC) with a post digital pulse shaping algorithm in FPGA. In this scheme, the analog front-end consists of a preamplifier using split-let topology followed by a variable gain amplifier. A multiple-point sampling ramp ADC is integrated to digitize the amplified pulse voltage signals into multiple point sampling data. The digital CR-RC
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shaping and digital trapezoidal shaping algorithms are implemented in a FPGA. Meanwhile, the triggers are digitized by a time-to-digital converter in the time channel of FPGA. A prototype ASIC is implemented in CMOS 0.35 μm mixed-signal process. The preliminary results have been obtained. The detection range of the gamma ray is from 11.2 keV to 550 keV. The linearity of the output voltage is less than 1 %. The gain of the readout channel is 40.2 V/pC. The test results show that the proposed front-end electronics is appropriable for PET imaging applications.