IDeF-X BD: A low noise dual polarity ASIC for the readout of Silicon and CdTe detectors

Our group has designed a family of ASICs dedicated to the readout of semiconductor detectors for space applications, named IDeF-X standing for Imaging Detector Front-end [1]-[3]. IDeF-X BD is a new member of the family. It has been optimized for the readout of low capacitor and low leakage current Silicon or Cd(Zn)Te detectors. IDeF-X BD has been designed in the standard AMS CMOS 0.35 μm process technology. Its power consumption is 3.3 mW per channel. The dynamic range of the ASIC is +/-70ke-. When no detector is connected to the chip, a 44 electrons rms ENC level is achieved after shaping with 6.8 μs peak time. Since IDeF-X BD is intended for space-borne applications in astrophysics, we evaluated its radiation tolerance and its sensitivity to single event latchup. We demonstrated that the ASIC remained fully functional without significant degradation of its performances after 300 krad and that the Latchup Linear Energy Transfer threshold was above 50 MeV/(mg/cm
²
). Good noise performance and radiation tolerance make the chip well suited for X-rays energy discrimination and high-energy resolution, “space proof,” hard X-ray-gamma-ray spectroscopy. It will be the readout ASIC of the silicon semiconductor diode detectors (SSDs) [4] in the STEP instrument [5] aboard the Solar Obiter ESA mission. The chip will fly on board the Solar Orbiter ESA mission in 2018.