Raised Source/Drain Dopingless Junctionless Accumulation Mode FET: Design and Analysis

We design and analyze a raised source/drain dopingless junctionless accumulation mode FET (RDJAMFET) on an intrinsic silicon film using charge plasma concept. This device does not have any physical doping or junctions. Using 2-D simulations, we demonstrate that by making use of the physical design parameters, the device can achieve reduced bandto-band tunneling-induced parasitic bipolar transistor action in the off-state as compared with the planar dopingless junctionless FET (DJFET) for sub-20-nm channel length devices. Further, the RDJAMFET has better gate control and shows significant improvements in terms of drain-induced barrier lowering, subthreshold swing, and I
_ON
/I
_OFF
as compared with the DJFET for sub-20-nm channel length devices.