Optimization of high-speed CMOS optical modulators with interleaved junctions

Modern microprocessors performance is often limited by the data delivery rate through conventional electrical interconnects. Optical interconnects offer a viable path to relieving this interconnect bottleneck and significantly increasing the capability of modern computers and datacenters. Here, we present a model and experimental validation for the high-speed performance of CMOS optical modulators using interleaved junctions. This model is benchmarked against two generation of CMOS modulators. The model uncovers the underlying bandwidth limitations of existing devices and suggests improvements that would enable 35 GHz optical modulators in microelectronics CMOS.