An XDL alternative for interfacing RapidSmith and Vivado

In recent years, the RapidSmith CAD tool [1] has been used with ISE to create custom CAD tools targeting Xilinx FPGAs. This tool flow was based on the Xilinx Design Language (XDL), a human-readable representation of a netlist that contains placement and routing information. The XDL interface also provided device representation files (XDLRC files), detailing the available resources of a given FPGA part. Using RapidSmith, a Xilinx design could be exported out of ISE at any stage of the design flow, manipulated in RapidSmith (logic modification, place, or route), and imported back into ISE to complete the remainder of implementation.