TeSHoP: A Temperature Sensing based Hotspot-Driven Placement technique for FPGAs

The rapid shrinking of the feature size in CMOS technology has significantly increased the power density of integrated circuits, leading to excessive temperature. Though online thermal management techniques such as DVFS and task migration can mitigate the temperature issue, but usually incur significant performance penalty. Therefore, it is crucial to optimize temperature at the design stage. In this work, we propose the TeSHoP, a Temperature Sensing based Hotspot-Driven Placement technique for FPGAs. Firstly, the un-optimized circuit along with a sensor network is run in FPGA to obtain the real temperature profile of the circuit. Then, based on the temperature profile, we proceed a one-off adjustment of the circuit placement for hotspot optimization. The optimization is modeled as a Hyper Minimum Bipartite Matching problem for solving. We implement the whole optimization flow in a real FPGA, with extension of the VTR-to-Bitstream tool. Experimental results on Xilinx Virtex-6 FPGA show that the reduction of peak temperature and the improvement of thermal uniformity can be up to 7.5°C and 13.9% respectively.