The Observation of Width Quantization Impact on Device Performance and Reliability for High-k/Metal Tri-Gate FinFET

In this paper, the impact of width quantization on device characteristic and stressing induced device degradation for high-k/metal tri-gate n/p-type FinFET was investigated well including electrical characteristic clarification and simulation. Carrier conduction in the trapezoidal shape Si-fin body of FinFETs is different for devices with different Fin bottom widths (W
_{Fin_bottom}
), which will impact the device performance and reliability. For n-type FinFETs, the experimental results show that the thinner W
_{Fin_bottom}
device performs better reliability under HCI stress due to higher inversion carrier density at the center of Si-fin channel. For p-type FinFETs under negative bias stressing, the thinner W
_{Fin_bottom}
device shows more serious degradation on drain current (I
_D
) and subthreshold swing (SS) with the increasing of stressing voltage due to larger electric field within the Si-fin and higher energy of inversion holes, while the thicker W
_{Fin_bottom}
device shows almost insensitively degradation with the variation of stressing voltage.