Gate stack solutions in gate-first FDSOI technology to meet high performance, low leakage, VT centering and reliability criteria

A unique gate stack solution has been found in gate-first FDSOI to meet at the same time high performance, low leakage, V
T
centering and reliability criteria for NMOS and PMOS with T
inv
=12.5Å and 14Å, respectively. Trade-offs between those characteristics are highlighted in this paper through process knob variations, including the interfacial layer (IL) formation, the IL surface treatment and the drive-in anneal temperature. The path allowing the construction of both low-V
T
high speed logic, reaching 7.2ps/stg FO3 ring oscillator delay at V
nom
=0.8V, and high-V
T
low leakage SRAM, achieving 3pA/cell standby leakage at V
nom
=0.8V, is demonstrated through gate workfunction engineering and gate leakage optimization. On top of this result, 5 years BTI and 10 years TDDB reliability lifetime were qualified at V
max
=0.945V, 125°C.