Impact of dynamic power supply noise induced by clock networks on clock jitter and timing margin

Timing closure on on-chip critical paths becomes more challenging as both data and clock jitter increase due to a large power supply noise. There have been intensive studies to model timing impact of power supply noise on the logic timing. Unlike the flip flops and combinational logics placed and routed randomly, the global networks including the clock buffers are usually custom design based so that they are placed regularly and densely. In the FPGAs, the multiple global networks up to 32 are routed in parallel as the chip size grows and number of transistors increase enormously. Since the clock buffers are placed very closely, a voltage drop of the power supply by the adjacent clock buffers switching makes the clock edge slow, when the clock edges of the victim and aggressors are aligned. This slowed down clock eats away setup the timing margin loss. The behavior of this noise impact is similar with signal to signal cross talk. In this paper, the supply noise impact due to the switching noise by the adjacent clock buffers is demonstrated by simulation and measurement. And it is described how to implement timing impact into STA (Static Timing Analysis) flow.