TCAD Simulation of Dual-Gate a-IGZO TFTs With Source and Drain Offsets

We investigate the effect of offset between source/drain (S/D) and gate electrodes (both top gate (TG) and bottom gate (BG)) on the electrical performance of dual-gate (DG) amorphous indium-gallium-zinc-oxide (a-IGZO) thin-film transistors (TFTs). The performance of the fabricated TFTs measured by BG sweep under various TG potentials are well fitted by TCAD simulation with the same density of states, which does not change with the device structure. The field-effect mobility is 15.5 cm
²
/Vs for the TFT with overlapped S/D electrodes, but it is less than 1 cm
²
/Vs for the offset TFTs. The low carrier concentration of ~10
¹⁶
cm
^-3
at the offset a-IGZO region is achieved by TCAD simulation, which increases the contact resistance, and thus induces current crowding and lower mobility in DG offset TFTs.