FPGA implementation of FIR filter using RADIX-2r

The fundamental operations of a Finite Impulse Response (FIR) digital filter are multiply and accumulate (MAC). Thus, the complexity of the filter largely depends on the complexity of the multiplier blocks. There exist several techniques to efficiently implement the multiplier using add and shift operations exclusively. Such designs are termed as multiplierless. The Single Constant Multiplication/Multiple Constant Multiplication (SCM/MCM) problem is finding the minimum number of additions and subtractions. This paper presents an FIR filter based on the RADIX-2
^r
recoding technique and implemented on a Field Programmable Gate Array (FPGA). The proposed filter performs better than a filter designed using generic multipliers.