Structural modification based netlist obfuscation technique for PLDs

Logic obfuscation is widely followed in intellectual property cores and chip designs as hardware protection mechanism against design security threats such as reverse engineering (RE), piracy, cloning, overbuilding, etc. In general, sequential obfuscation has two modes of operation such as obfuscated and functional modes. Finite state machines (FSM) are being used to implement the mode control. When a specific sequence of input vectors is applied during power up for user authentication, the circuit will enter into functional mode. Otherwise, FSM remains in obfuscated mode and do not perform the intended functionality. In general, hardware obfuscation technique is applicable to all programmable logic devices. However, we applied the structural modification based netlist obfuscation methodology to field programmable gate array devices. The software implementation of sequential obfuscation is performed for a set of ISCAS'89 benchmark circuits using Libero IDE v9.1 on Actel device. As simulation/ structural analysis are the conventional methods to perform RE, we aimed to achieve a high percentage of simulation / structural mismatch during RE. We presented two scenarios of obfuscation: 1) For better structural mismatch during RE, insertion of obfuscation cells at different numbers of high fanout (HF) nets with minimum initialization sequence length (L). As per the designer's area constraint, the total number of nets to be obfuscated is chosen. 2) For better functional simulation mismatch during RE, FSM with different L values is included in the design with a minimum number of obfuscation cells. The initialization sequence length is decided concerning the system clock cycle (i.e. delay constraint). Based on the control signals derived from FSM, the values at HF obfuscated nets are decided. That is, the circuit executes the required functionality only in the functional mode. Hence, the simulation/ structural RE complexity of PLDs is improved. This paper discusses the simulation results of above-discussed scenarios using area, delay and power measurements.