Design considerations for digitally controlled buck converters with large input transients

While digital control has achieved success in various power electronic applications, data conversion remains a primary challenge and limitation compared to conventional analog methods. In particular, tradeoffs among resolution, switching frequency, and power consumption of digital pulse-width modulation (DPWM) blocks limit performance, particularly in high conversion-ratio applications. Analog-digital conversion is also challenging when line-voltage feedforward techniques are applied as it requires high speed, accuracy, and in some cases exposure to voltages exceeding the rating of deep-submicron CMOS technologies. This work explores tradeoffs in power consumption of counter/delay-line DPWM circuits, implemented in CMOS, and derives an optimization method to segment the bit allocation among the counter and delay line components. A method for line-voltage feedforward is also presented that can instrument and quantize transients on the supply voltage without direct exposure of low voltage devices to the supply. An automotive 48V:7V application is considered.