Self-aligned double patterning for vacuum electronic device fabrication

We developed a fabrication process that incorporates self-aligned double patterning to produce nanoscale electrostatic grids in close proximity to an electrode. These nanoscale grids can be used to mitigate the effects of space charge in the inter-electrode region of a thermionic converter and thereby improve conversion efficiency. The nanoscale dimensions and low fill factor of the grid help to prevent loss by limiting detrimental electron absorption. Compared to other advanced lithographic techniques used to pattern nanoscale features with similar, sub-100 nm dimensions, self-aligned double patterning is cost-effective, wafer-scale, and allows for rapid prototype iteration.