An Efficient FPGA Design and Performance Testing of the ACE Algorithm for PAPR Reduction in DVB-T2 Systems

Active constellation extension (ACE) is one of the common algorithms for peak-to-average power ratio reduction in digital video broadcasting-second generation terrestrial (DVB-T2) systems. In this paper, we study the implementation of the ACE algorithm for DVB-T2 on field programmable gate array (FPGA) platforms. For this purpose, a general hardware architecture with two parallel channels is first proposed. The proposed architecture is based on 16-bit fixed-point representation which can achieve a tradeoff between numerical accuracy and hardware cost. Moreover, the pipelining design is adopted in some units and arithmetic components of the proposed architecture, with respect to enhancement of working frequency. Aiming at a specific DVB-T2 system, the proposed architecture is implemented in a low-cost FPGA platform. Implementation results indicate that the fixed-point FPGA design involves less hardware overhead, and can run at a clock of up to 120.6 MHz and achieves a maximum throughput of 513 Kb/s. Finally, the performances of the fixed-point FPGA design are verified on a laboratory prototype. Experimental results demonstrate that the proposed fixed-point FPGA design provides an accuracy performance that is very close to that of floating-point simulation counterpart.