Real Time Multiplication And Division For VLSI DSP

This paper describes recent developments in VSLI design for real-time digital signal processing. In particular, designs for integer multiplication for use in FIR, IIR and lattice filters and floating point division applicable to both adaptive filtering and standard deviation computations, will be talked about at length. Emphasis here is on the internal architectures of the arithmetic units not on their applications. The research presented in this paper has been proven reliable and feasible by completing the design, lay-out, and fabrication in silicon.