A Graph-theoretic Approach For One-dimensional Logic Gate Assignment Of Vlsi Circuit Layout

This paper proposes a new approach for the one-dimensional gate assignment problem. By converting the original problem to a graph G, we transform the gate assignment as a qraph-theoretic problem. A minimum-cut algorithm is applied to the graph G to find the node- ordering which corresponds to the gate assignment in the original problem. This new approach is shown through comparison with published examples to produce optimal solutions.