Exploitation Of Parallelism In Vlsi Array Testing

A systematic procedure for testing of VLSI reconfigurable arrays is proposed. The system is divided into three layers. Layer I includes configuration control circuit and busses to broadcast configuration information. Layer II covers the interconnection network and layer III contains the rest of the array including cell functional units. Testing (fault location) is performed from the lowest layer to the highest layer. Only the fault-free parts identified are used in the subsequent layer testing. Due to this separation, parallelism in testing has been exploited considerably. The algorithm can be realized with very low hardware overhead.