RAM-JET: Towards The Removal Of Multiplicative Compleidty In Digital Signal Processingvlst Arclutectures

The concept of a programmable systolic cell is introduced that allows finite ring arithmetic to be performed using bit-level systolic arrays. The motivation for this work is the recent introduction of a fixed coefficient bit-level inner product step processor operating over a finite ring (BIPSPm). From design and fabrication experiments performed on this cell, it is clear that it represents a major step forward in the implementation of very high speed fine-grained DSP algorithms. The remarkable properties of the cell are the ability to implement fixed product multiplication with only twice the area overhead of a bit-level binary adder, and yet provide operation at slightly higher throughput rates. The cell also has low overhead associated with error detection, and an entire array of an arbitrary number of cells in a linear pipeline, can be tested with only 32 test vectors in the time taken to pass the vectors through the array. This paper discusses a programmable system that will operate with a modified cell, to allow arbitrary algorithms to be implemented without incurring the overhead associated with general multiplication. Rather than seek algorithms that minimize multiplication, we can rather seek algorithms that provide a homogeneous VLSI structure.