Considerations For Hardware Implementations Of Neural Networks

In constructing electronic hardware neural networks, algorithms as well as circuitry must be designed in a manner tolerant of limitations imposed by the implementation medi- um. Two development efforts are described in which hardware and algorithms are designed to operate within space, dynamic range, and noise constraints of analog CMOS VLSI technology. The performance of a single-layer feedback network incorporating simple binary interconnects is extended by using an analog prompt method. A "building block" approach for the design of multilayer feedforward networks is made possible by a new learning algorithm tolerant of hardware limitations.