Optimized Power Delivery for 3D IC Technology Using Grind Side Redistribution Layers

This paper addresses the issue of delivering power to high performance 3D stacks such as a processor on cache stack. Through Silicon Vias (TSVs) with their associated keep out zones (KOZ) occupy only a small fraction of the die (<;1%) but can cause much larger design inefficiencies in the lower strata. We show that integrating the power TSVs in the thin wire levels (M1 for example) of the hierarchy limits the amount of current deliverable by a TSV to well below its capabilities due to electromigration limitations of the thin wire level connection to the TSV. We propose a scheme whereby a single TSV is fed current from four regular controlled collapse chip connection (C4) - laminate connections. When the TSV is integrated at the fat wire level it can deliver this 1A to a system of eight μ-bumps that deliver the current uniformly to the upper strata. We also show that small cylindrical TSVs while capable of delivering power suffer from excessive IR drops but a larger annular TSV is a more optimal solution. Finally, we show that integrating the TSV with the "Super Fat" wire levels results in an optimal power grid with minimal IR drop and uniform power distribution.