A Prospective Low-k Insulator for Via-Last through-Silicon-Vias (TSVs) in 3D Integration

Through-silicon-vias (TSVs) processes, which provide direct electrical paths between chips which results in shorter interconnect length, improved performance and better power efficiency, have been intensively investigated for vertically-stacked 3D semiconductor devices. Low-k materials have been considered in the literature for the insulation layer of the TSV interconnection since its low dielectric constant can benefit in minimizing the signal delay, lowering the power consumption, reducing the cross-talk between neighboring paths, as well as improving the electrical performance by reducing the capacitive coupling. Owing to their low Young's modulus, polymer low-k materials can also serve as an internal stress buffer layer and reduce the process-induced thermal stresses around TSVs which are caused by the mismatch of thermal expansion between constituent materials, and would produce serious reliability issues such as silicon cracking or performance degradation of devices. In this work, we investigate the fundamental and essential properties of this potential material, i.e. Parylene-HT, for use as an insulation layer/liner for the application of 3D integration (i.e., CMOS-LSI staking). A complete data set on the technology assessment of Parylene-HT as a prospective low-k insulator for use with via-last TSV processes is presented. In particular, evaluation results on the insulating behaviors (i.e., leakage currents and capacitances) of metal-insulation-semiconductor (MIS) samples with Parylene-HT insulation of thickness 1 μm are presented. The same structures with 1 μm of SiO
₂
as the insulation layer were also characterized for comparison. Experimental results show good insulation performance of Parylene-HT after being annealed at different temperatures, even up to 350°C, the thermal budget of most of the BEOL processes.