Reliability Demonstration of an Ultra-Thin Core (UTC) Large Die, Large Laminate Package

The demands for the next generation organic laminate materials include high speed signal (HSS) performance enhancements as well as improvements in bond and assembly processing yields. A typical organic laminate structure consists of one or more layers of build-up and copper on each side of a copper clad core. The industry has recently incorporated coreless laminates mostly in small die packages to reduce layer counts and cost. However, especially for large die, large laminate form-factors, coreless packages require addressing manufacturing challenges due to warp, and concerns with chip package interaction (CPI), due to their higher coefficient of thermal expansion, CTE. A core, which provides stiffness, is beneficial to reduce high thermal warpage, especially in large body laminates. Also, to improve the mechanical performance and thermal-mechanical reliability, a lower composite laminate CTE is preferred. A low CTE core in addition allows lowering the composite CTE and is used to mitigate CPI. However, the use of thick cores increases build-up layer count due to wiring constraints and consequently increases laminate cost and thickness. Also process costs associated with laminate drilling of the plated through holes (PTH) increase. The benefit tradeoff between cored laminates and coreless can be satisfied by examining an Ultra-Thin Core (UTC) laminate package. UTC laminates offer the advantages of low cost and high speed signal transmission of a coreless laminate while overcoming its high CTE and warp concerns by utilizing a low CTE core with thickness less than 300um. Such UTC structure allows for a robust PTH formation process, developed uniquely by Kyocera. Large body size UTC laminates can be introduced into module manufacturing without any special fixturing or processing that are often needed with coreless packages. This paper focuses on the assembly, characterization, and reliability stress results of UTC laminates used to assemble large die, large laminate (LD/LL) SCM packages. C4 solder bumps are subjected to shear strains and fatigue degradation during thermal cycling and power cycling in field operation. Such shear strain is proportional to the DNP (distance from neutral point) and therefore solder fatigue fails often occur at the corner C4's first. Higher laminate composite CTE imposes additional shear strain to the C4 interconnect bumps. The UTC core helps to reduce the composite CTE and improve reliability. The flip chip package studied was a 6-2-6, 55mm laminate structure with 200um core and solder resist opening defined C4 bumps. Comparison is made with a 6-2-6, 55mm laminate with 400um core (thin core) and C4 solder resist opening. A CPI test chip was mounted on the low CTE UTC Ball Grid Array (BGA) laminate using traditional bond and assembly (BA) processes and fixtures. This was followed by liding with a Thermal Interface Material (TIM) between the test chip and a heat spreader, and an elastomer sealant between the laminate and the heat spreader. The sub-assembly was then tested, attached to a thermal card for power and signal connection. Examination of the C4 interconnect after 1000 cycles of deep thermal cycling (DTC) and biased Highly Accelerated Stress Test (HAST) of 110°C, 85% Relative Humidity (RH), and 3.6 volt bias revealed good C4 interconnect reliability of UTC laminate packages, comparable to the traditional 400um core laminates. Characterization and construction analysis of the package, and model and data comparison with traditional thin core and coreless packages will be presented.