The Development and the Integration of the 5 µm to 1 µm Half Pitches Wafer Level Cu Redistribution Layers

The original purpose of the Re-Distribution Layers(RDL) was to assist in the adaption of metal bumping and flip chip packaging technologies, by the addition of the metal and dielectric layers onto the wafer surface to re-route the legacy designed irregular peripheral I/O layout, into a new area array bond pads layout to facilitate a balanced metal bumps and flip chip bonding. The redistribution layer technology required polymeric/organic thin film (e.g. BCB, Polyimide, PBO) as insulator and with semi-additive metallization scheme (often Cu pattern plating) to serve rerouting purpose. The redistribution trace technology, other continuing its association with bumping and flip chip packaging and wafer level chip scale packaging (WLCSP), now extend its application into advanced packaging technologies, such as fanout wafer level packaging (FO WLP) and various TSV-less, substrate-less multiple chip integration, that to drive the cos teffective miniaturization of system-in-package (SiP) application. The Cu RDL that in production, the line width/ line spacing are 10 micrometer (μm)/10 μm which make the full pitch of 20 μm and half pitch of 10 μm. For the sake of the simplicity, half pitch will be used as index for benchmarking. In the area of the multiple chip integration or SiP applications, particularity those that do not use laminate substrates, RDL play an important role to interconnect multiple ICs with IO counts in thousands to tens thousands, replacing the role of multiple build up layers of the laminate substrate, thus 10 μm half pitch no longer meet the need of connecting high density IO and there is driving force to scale down RDL half pitch and increase number of RDL layers, from single layers to two to three layers of metal traces excluding under bumping metals(UBM) for attaching BGA balls. PWB industry is under going the similar efforts to target to put substrate with 5 um linewidth into market. In this paper, development efforts in scaling down RDL half pitch, with existing polymeric insulting film and Cu pattern plating will be revealed. It is discovered that scaling from 10 to 3 μm posed no significant technical difficulties with existing tools that are in production, as long as the Cu thickness are proportional shrunk to keep the width/ height aspect ratio. Below half pitch of 3 μm, it would be difficult to make such fine pitch layer on top of other layers, since the topography of multiple RDL with any planarization, that is out of the depth of focus (DoF) range of 2 μm and 1 μm, and these 1 μm / 2 μm half pitches, would be limited to as the first RDL in the multiple RDL scheme. Cu dual damascene technology with CVD dielectric film (Si oxide, Si nitride) that were commonly used in the modern IC fabrication fab capable of the advanced node (90nm and beyond), was also phased in and demonstrated that up to three levels of 1um Cu RDL are feasible with this technology. Furthermore, hybrid integration of the fine line CVD RDL with the RDL with polymeric dielectrics is also demonstrated.