A Cost-Effective, CMP-Less, Via-Last TSV Process for High Density RDL Applications

The continual downscaling of CMOS transistors, as predicted by Moore's Law, has faced tremendous challenges in terms of performance and cost reduction. Through Silicon Via (TSV) technology provides an alternative "More than Moore" solution for system level integration, resulting in smaller form factor, reduced power consumption and large bandwidth for higher data transfer rate. Via-last (VL) TSV from wafer backside is a relatively simpler and more cost-effective way to enable 2.5D/3D heterogeneous integration. However, there are challenges involved with wafer processing on temporary bonded wafers. In addition, for high performance applications, multiple RDL layers with fine line width and space are needed. This paper presents a cost effective CMP-less via-last (VL) TSV integration flow, which enables Cu RDL with fine feature size of 2μm and below. For demonstration, 10μm x 40μm via-last (VL) TSVs are fabricated. Electrical and physical characterizations are performed to verify the feasibility of this work.