Finite Element Modeling of C4 Cracking in a Large Die Large Laminate Coreless Flip Chip Package

BGA substrates made of organic materials are now industry standard as they provide significant advantages over the ceramic dielectric-based predecessors in manufacturing cost and electrical performance. A typical organic laminate structure consists of one or more layers of build-up and copper on each side of a copper clad core. In recent years, the industry has also introduced the concept of organic build up laminate without a core layer, more commonly known as coreless laminates, to overcome the disadvantages of the plated through holes (PTH) in the core structures, which specifically drive restrictions in wiring capability and retard signal transmission speed. Although coreless laminates offer better opportunity for low cost and high speed transmission package designs, they are usually associated with high thermal warpage due to the lack of reinforcement provided by a rigid core layer. This becomes particularly challenging in large body size substrates. Furthermore, the composite coefficient of thermal expansion (CTE) of a coreless laminate is significantly higher than cored alternatives, which leads to higher chip package interaction (CPI) stresses. This paper focuses on the reliability issues of C4 bump cracking in a large die large laminate (LDLL) coreless flip chip package. C4 solder bumps are subjected to shear strains and fatigue degradation during thermal cycling and power cycling in field operation. Such shear strain is normally proportional to the DNP (distance from neutral point). Therefore solder fatigue often occurs at the corner C4's first. To further increase the reliability concern, the composite CTE's of coreless organic laminates are higher than cored laminates, which impose additional shear strain to the C4 interconnect bumps. Two coreless flip chip packages, with pad defined C4 bumps and solder mask opening defined C4 bumps, will be examined in this paper. Comparison of fail counts after 1000 cycles of deep thermal cycling (DTC) reveals that pad defined C4 bumps are more robust than solder mask opening defined C4's. Failure analysis of the cracked C4 bumps will be illustrated. The thermal-mechanical modeling methodology will be outlined and verification of simulations with experimental results will be presented. Parametric studies on the effect of C4 bump geometry, laminate material properties and other form factors on C4 fatigue will be discussed. A predictive model for C4 solder joint fatigue in coreless flip chip packages will be proposed.