Nanocrystalline ZnO TFTs Using 15-nm Thick Al2O3 Gate Insulator: Experiment and Simulation

Thin-film transistors were fabricated using 45-nm thick ZnO deposited by pulsed laser deposition and 15-nm thick Al
₂
O
₃
gate insulator deposited by atomic layer deposition. A 1-D model with a constant density of interface states above and below the conduction band edge is used to explain the current-voltage characteristic. This model does not create distortion of transconductance versus gate voltage at low gate voltage that can be created by exponential tail or Gaussian distributions of interface states. The “subthreshold” regime is at the top ZnO surface away from the bottom gate, but subthreshold swing is controlled by interface states at the ZnO/Al
₂
O
₃
bottom interface. The observed increase in mobility with gate voltage is delayed by filling of the interface states above the conduction band edge. Interface state filling and a rapid increase in mobility with increased gate voltage produce an apparent large threshold voltage as extrapolated from a linear fit to current measured at large gate voltage. The difference between threshold voltage and turn-off voltage is an important figure of merit (FOM) that should be kept as small as possible. In this paper, FOM is 2.5 and 1.8 V for 0.1 and 6 V drain voltage, respectively.