A 0.035-pJ/bit/dB 20-Gb/s Adaptive Linear Equalizer With an Adaptation Time of 2.68 $\mu\text{s}$

A 20-Gb/s adaptive linear equalizer with a coefficient fast-converging method is presented. By using the asynchronous sampling technique, the power dissipation of the circuits, realizing the adaptation method, can be reduced. However, the equalization coefficients require a considerable amount of time to be determined. To shorten the asynchronous sampling time, the high-frequency gain of the linear equalizer is calibrated prior to the low-frequency one. With a 20-Gb/s pseudorandom binary sequence of 27 - 1, the measured bit-error-rates are all less than 10-12 for channel loss from -7.98 to -18.3 dB. Moreover, the equalization coefficients are determined within 2.68 μs. Fabricated in a 40-nm CMOS technology, this equalizer totally consumes 12.8 mW from a 1.1-V supply, of which only 4.9 mW dissipates in the circuits, realizing the proposed method. The calculated figure-of-merit is 0.035-pJ/bit/dB.