A 25NS CMOS Electrically Erasable FPLA

Recently, several CMOS PLDs were reported using nonvolatile memory technologies for array implementation. However, the architecture of these CMOS PLDs are limited in only one programmable array feeding into a group of fixed OR gates. Therefore, the efficiency of its logic integration is greatly limited due to lack of product term sharing capability. This paper will describe a 25ns, 50mA CMOS Programmable Electrically Erasable Logic Device with both reconfigurable AND array and OR array. High speed is achieved by separating logic path from program/verify circuit, and a bootstrapped single-ended sense amplifier.