CMOS 0.5-micron unified digital array using full E-beam lithography

A masterslice (gate array) design can provide fast turn-around time on chip fabrication by sharing a pre-fabricated common array, but typically results in low circuit density and performance because of limited freedom of wiring the fixed transistor array. On the other hand, a masterimage (standard cell) design can achieve higher circuit density and performance by customizing circuit layout and placement, and by patterning the polysllicon lines as an additional wiring level. However, the circuit customization makes every masterimage layout exclusive from the beginning of the fabrication, and thus results in a much longer fabrication time compared to a masterslice design.