Low-power clock-deskew buffer for high-speed digital circuits

An IC containing four clock deskew buffers using the delay-locked-loop technology has been fabricated in a 0.6 /spl mu/m single poly double metal CMOS process. The core chip area is 0.9/spl times/0.9 mm/sup 2/. The maximum operating frequency is 80 MHz, and the total power dissipation of the four deskew buffers is 59 mW for a 3 V supply voltage. The maximum clock skew after deskewing is less than 300 ps, and the peak-to-peak clock jitter is less than 170 ps. The deskew range is 0.5-3.8 ns.